EECS168 Introduction to VLSI Design - Winter 2015

Course Information

Instructor:

Sheldon Tan (stan@ece.ucr.edu)
Office Hours: Thursday 3:00-4:00 PM or by appointment.
Office:WCH 424

Lecture:

TR 6:40-8:00 PM, Alfred M. Boyce Hall (BOYHL) 1471

Lab:

Section 021, W 6:10-9:00 PM, CHUNG 125

Section 022, F 11:10-2:00 PM, CHUNG 125

Teaching Assistants

David Shin (hshin013@ucr.edu) for section 021

David Shin (hshin013@ucr.edu) for section 022

Office Hours: W11:00am to 12::00pm, WCH 109

Textbook:

Modern VLSI Design: IP-Bbased Design by Wayne Wolf, Fourth Edition, Prentice Hall PTR
Amazon Website
Pearson High Education Website

Grading:

Grading for the class will be performed on an individual basis. You will not be competing with the other students for your grade. If all students do well in the class, it is possible everyone will get an A. Your grade is only dependent on the effort you put into the class. Letter grades will be assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an F. 

The grading will be based on a weighted sum as follows: 

 

30%		Final
20%		Midterm
10%		Quizzes
10%		Homeworks
30%		Lab Assignments

 

Policies:

Punctuality: Please arrive on-time to class.

Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own.

Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand.

Lab Attendance: Lab attendance is mandatory for the entire lab period during which you should be working on course related material. If you finish a lab assignment early, work can always work ahead on the next assignment.

Class Mailing List: The class mailing and newsgroup in the ilearn will be used for all course related correspondence such as course announcements. Furthermore, please address all course related questions regarding lectures, homework, labs, etc. to the course mailing list or newsgroup.

Cell Phones: Please turn your cell phone off before you come to class.

Lecture Schedule (all the slides will be available after the lecture in ilearn)

SUBJECT TO CHANGE

 

Week 1	Course Overview, Introduction to VLSI Design, (Chapter 1); Fabrication, Transistor Structures, Basic Transistor Behavior, (Chapter 2); Transistor Characteristics, (Chapter 2),
Week 2	Designs Rules and Stick Diagrams, (Chapter 2); Combinational Logic Functions and CMOS Logic Gates, (Chapter 3)	HW1 given
Week 3	Electrical Properties of Combinational Gates, (Chapter 3); Quiz 1 on the second lecture this week.
Week 4	Electrical Properties of Combinational Gates (continued), (Chapter 3);Wire Delay, Buffer Insertion, Etc., (Chapter 3);
Week 5	Psuedo nMOS Gates, DCVS Logic, Domino Gates, (Chapter 3); Layout, Channel Routing, Simulation, (Chapter 4).	HW 2 given
Week 6	Combinational Network Delay, Logic Optimization (Chapter 4); Transistor Sizing, (Chapter 4); Interconnect Design, Crosstalk, Power Optimization (Chapter 4).
Week 7	midterm 2; Switch Networks, Combinational Testing, (Chapter 4); Memory Elements, Basics of Sequential Machines, (Chapter 5); Clocking Disciplines, (Chapter 5). Midterm on the second lecture of this week.	HW 3 given
Week 8	Sequential Machine Design, (Chapter 5); State Assignment, Power Optimization, Design Validation, Sequential Testing, (Chapter 5
Week 9	FPGA Fabric Architectur(Chapter 6); SRAM-based FPGA Fabrics (Chapter 6)	HW 4 given
Week 10	Shifters, Adders, ALU, (Chapter 6); Multipliers, (Chapter 6); Memories, Datapaths, PLAs, (Chapter 6)
Final week	Final: March 14 (Saturday), 2014 7:00pm to 10:00pm (same room as the lecture room)

 

Homework (should be submitted electronically into ilearn)

Homework 1:

Homework 2:

Homework 3:

Homework 4:

Quizzes

Lab Schedule

Labs must be finished on-time. Late labs will not be accepted. A lab report, using the specified lab report format is required for all lab assignments, including tutorials, and is due at the beginning of the following lab period after the lab is due. Individual labs may also require additional information such as schematics, layout, or a summary of results. Please be sure to include this information in your lab report. Your lab report will count for 20% of each lab score.

Week	Date	Description	Points
Week 1		Lab/Tutorial 1 - Introduction to Cadence Schematic Design/Simulation	50
		Lab/Tutorial 2 - Introduction to Cadence Layout Design Demo and Lab Report due at the end of lab.	50
Week 2		Lab 3 - NAND Gate Transistor/Layout Design	100
		Lab 3 (Continued) - NAND Gate Transistor/Layout Design Due at the end of lab.
Week 3		Lab 4 - 4-bit Adder Design
		Lab 4 (continued) - 4-bit Adder Design	200
Week 4		Lab 4 (Continued) - 4-bit Adder Design
		Lab 4 (Continued) - 4-bit Adder Design Due at the end of lab.
Week 5		Lab 5 - 1-bit SRAM Memory Cell Design	100
		Lab 5 (Continued) - 1-bit SRAM Memory Cell Design Due at the end of lab.
Week 6		Lab 6 - 4-bit SRAM Shift Register	200
		Lab 6 (Continued) - 4-bit SRAM Shift Register
Week 7		Lab 6 (Continued) - 4-bit SRAM Shift Register
		Lab 6 (Continued) - 4-bit SRAM Shift Register Due at the end of lab.
Week 8		Lab 7 - Field Programmable Gate Array (FPGA) Configurable Logic Block (CLB) Design	300
		Lab 7 (Continued) - FPGA CLB Design
Week 9		Lab 7 (Continued) - FPGA CLB Design
		Lab 7 (Continued) - FPGA CLB Design
Week 10		Lab 7 (Continued) - FPGA CLB Design
		Lab 7 (Continued) - FPGA CLB Design Due at the end of lab.