Elsevier just released the new CiteScore and Impact Factor for the Integration, the VLSI Journal, the CiteScore (CS) is 2.6, Impact Factor (IF) is 1.214. This is a good improvement from 2.2 for CS and 1.15 for IF from 2018. Prof. Tan was the Editor in Chief for Integration since 2016. CiteScore of a journal...
Three PhD students from VSCLAB, Mohammadamir Kavousi, Yibo Liu and Maliha Tasnim, were accepted into the DAC Young Fellows Program. They will attend the first virtual 57th Design Automation Conferences in July, 2020. Congratulations on them.
Most of senior PhD students in VSCLAB headed to industry intern jobs in summer 2020. Have funs and enjoy! Sheriff Sadiqbatcha will work for Intel Corp, Shaoyi Peng will work Cerebras System, an AI chip startup, Han Zhou will work for PrimePower group in Synopsys, Jinwei Zhang will work for Spectre group in Cadence, Wentian...
Sheriff Sadiqbatcha and Jinwei Zhang's work on machine learning based hotspot identification for commercial multi-core processors has been accepted by IEEE Transaction on CAD, the primary journal in EDA area. This work presents a significant advance for transient hotspot identifications using latest recurrent neural networks for commercial multi-core processors. The method can be used for...
Visiting Ph.D. student, Liang Chen's work on new semi-analytic solution for combined electromigration and thermomigration for general multi-segment interconnect wires has been accepted by IEEE Transaction on Computer-Aided Design. This work show the thermomigration can plays a significant roles on EM-failure and we developed a new approach to consider the Joule heating induced temperature spatial...
Prof. Sheldon Tan received a three-year $500K award (CCF-2007135) from National Science Foundation for exploring data-driven and deep learning based approaches to addressing the VLSI reliability and robust chip design. Recently machine learning, especially deep learning is gaining much attention due to the breakthrough performance in various cognitive applications. Machine learning for electronic design automation...
VSCLAB released the EMspice -- coupled EM-IR drop analysis tool for full-chip EM and IR check and sign-off. This is first tool to perform the full-chip EM-IR drop co-simulation to assess the EM-induced IR drop at specific targeted lifetime. The research work, leaded by Ph.D. student Zeyu Sun, has been published recently in IEEE Transaction...
April 23, 2020, Ph.D. student Sheriff Sadiqbatcha won the prestigious Dissertation Year ProgramFellowship award from UCR graduate division to support his Ph.D. study at UCR. The award will provide one quarter stipend support for Sheriff. This is highly competitive award for UCR phd graduate students.
We recently developed a new real-time differential virus transmission model, which can give more accurate and robust short-term predictions of COVID-19 transmitted infectious disease with benefits for near-term projection. The new model is based on well-accepted enhanced Susceptible-Exposed-Infected-Removed (SEIR) virus transmission model. But as the parameters of the improved SEIR models are trained by short...
3/12/2020, Ph.D. student Zeyu Sun successfully defended his thesis titled "Physics-based Electromigration Modeling, Analysis and Optimization"! Congratulations on Zeyu. Zeyu published several important works on the EM modeling such as new voltage based EM immortality checking and EM saturation volume estimation methods. He is also the developer of EMSpice for coupled EM-IR analysis for on-chip...
The GLU 3.0 solver, which is the GPU-based parallel sparse LU solver and was developed by Ph.D. student Shaoyi Peng, has been accepted to publish in IEEE Design and Test, which is one of top journals in the electronic design automation area. This paper introduced the latest version of GLU solver, GLU 3.0, which features...
Prof. Sheldon Tan won the ASPDAC Prolific Author Award in the IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC) 2020 in Beijing. This award is for authors who have published more 25 papers in ASPDAC. Prof. Tan published 37 papers since 1999, which ranked him as #6 in the prolific author list at http://aspdac-hall.nics.cc...
Ph.D. student Chase Cook successfully defended his Ph.D. thesis titled "Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design". Chase will join Intel Corporation after graduation. Congratulation on his hard works and successful defenses and we wish him the best in his feature endeavor.
Visiting Ph.D. student, Liang Chen's work on fast analytic solution for EM analysis for general multi-segment interconnect wires has been accepted by IEEE Transaction on VLSI. Congratulation on Liang! L. Chen, S. X.-D. Tan, Z. Sun, S. Peng, M. Tang and J. Mao, “Fast analytic electromigration analysis for general multi-segment interconnect wires”, IEEE Transactions on...
UCR is ranked number 5 in electronic design automation (EDA) related research in the latest CS ranking ahead Berkeley and MIT. Please see http://csrankings.org/#/index?da
GLU 3.0, the latest GPU-accelerated sparse parallel LU factorization solver, is released today. GLU 3.0 is a significant improvement over existing GLU 2.0 and GLU 1.0 in terms of performance and numerical stability. The new GLU solver will be beneficial for many high performance computing applications as sparse LU factorization is one of core computing...
Ph.D. student, Chase Cook's work on the GPU-based Ising computing to solve the graph max-cut problem, has been accepted for publication in Integration, The VLSI Journal. This is the first publication from VSCLAB on the Ising based computing based on GPGPU. It is an important mile stone at VSCLAB for GPU-based Ising computing for solving...
Undergraduate student researcher, Karina Rowe, won the prestigious BCOE's Alan Van Tran Student Award. Karina worked in the VSCLAB from Sept. 2018. She was supported by NSF REU fund for her research study at VSCLAB. She worked with Ph.D. student Chase Cook for the EM-based aging sensor design for hardware security and Ising computing for...
NSF funded a new collaborative research and student training program at VSCLAB at UC Riverside. The new project is tittled "IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design", OISE-1854276 starting April 1st, 2019. See detailed at https://www.nsf.gov/awardsearch/showAward?AWD_ID=1854276&HistoricalAward... This new IRES Track I program is devoted to collaborative...
Ph.D. student, Sheriff Sadiqbatch's TCAD paper on the novel EM acceleration technique has been accepted. The work represents a novel reservior-sink based EM acceleration technique, which can allow the EM acceleration without leading to other long-term relibility effects such as TDDB, HCI etc. The paper informaiton is as follows: S. Sadiqbatcha, Z. Sun and S...
