Ph.D. student Chase Cook successfully defended his Ph.D. thesis titled "Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design". Chase will join Intel Corporation after graduation. Congratulation on his hard works and successful defenses and we wish him the best in his feature endeavor.
Visiting Ph.D. student, Liang Chen's work on fast analytic solution for EM analysis for general multi-segment interconnect wires has been accepted by IEEE Transaction on VLSI. Congratulation on Liang! L. Chen, S. X.-D. Tan, Z. Sun, S. Peng, M. Tang and J. Mao, “Fast analytic electromigration analysis for general multi-segment interconnect wires”, IEEE Transactions on...
UCR is ranked number 5 in electronic design automation (EDA) related research in the latest CS ranking ahead Berkeley and MIT. Please see http://csrankings.org/#/index?da
GLU 3.0, the latest GPU-accelerated sparse parallel LU factorization solver, is released today. GLU 3.0 is a significant improvement over existing GLU 2.0 and GLU 1.0 in terms of performance and numerical stability. The new GLU solver will be beneficial for many high performance computing applications as sparse LU factorization is one of core computing...
Ph.D. student, Chase Cook's work on the GPU-based Ising computing to solve the graph max-cut problem, has been accepted for publication in Integration, The VLSI Journal. This is the first publication from VSCLAB on the Ising based computing based on GPGPU. It is an important mile stone at VSCLAB for GPU-based Ising computing for solving...
Undergraduate student researcher, Karina Rowe, won the prestigious BCOE's Alan Van Tran Student Award. Karina worked in the VSCLAB from Sept. 2018. She was supported by NSF REU fund for her research study at VSCLAB. She worked with Ph.D. student Chase Cook for the EM-based aging sensor design for hardware security and Ising computing for...
NSF funded a new collaborative research and student training program at VSCLAB at UC Riverside. The new project is tittled "IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design", OISE-1854276 starting April 1st, 2019. See detailed at https://www.nsf.gov/awardsearch/showAward?AWD_ID=1854276&HistoricalAward... This new IRES Track I program is devoted to collaborative...
Ph.D. student, Sheriff Sadiqbatch's TCAD paper on the novel EM acceleration technique has been accepted. The work represents a novel reservior-sink based EM acceleration technique, which can allow the EM acceleration without leading to other long-term relibility effects such as TDDB, HCI etc. The paper informaiton is as follows: S. Sadiqbatcha, Z. Sun and S...
Ph.D. student, Zeyu Sun's paper on the EM saturatiom volume estmation for general interconnect wires has been accpeted by TVLSI: Z. Sun, S. Sadiqbatcha,H. Zhao, and S. X.-D. Tan, “Saturation volume estimation for multi-segment copper interconnect wire”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press).
