NSF funded a new collaborative research and student training program at VSCLAB at UC Riverside. The new project is tittled "IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design", OISE-1854276 starting April 1st, 2019.

See detailed at https://www.nsf.gov/awardsearch/showAward?AWD_ID=1854276&HistoricalAward...

This new IRES Track I program is devoted to collaborative research to develop new algorithms and techniques for reliability-aware physical design and optimization of VLSI systems. U.S. students will be trained through collaborative research between two teams -- UCR's VLSI System and Computation Research Lab (VSCLAB) and Tsinghua University's Design Automation Lab.   

The IRES collaborative project will produce important research advances through joint development of efficient algorithms and design methodologies to address the grand challenges of reliability-aware physical design and optimization of VLSI systems. The PIs will look at the most severe and challenging aspects of verification and design problems of silicon CMOS based integrated systems in current and coming 10nm/7nm nodes: modeling, analysis of long-term interconnect reliability effects such as electromigration (EM), time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and reliability-aware physical design and optimization.