Breadcrumb

EE/CS 168 Winter 2018: Introduction to VLSI Design

Instructor

Sheldon Tan (stan@ece.ucr.edu)

Office Hours: Thursday 2:00-3:00 PM or by appointment.

Office:WCH 424

Lecture

TR 6:40-8:00 PM

Winston Chung Hall 138

Lab

Section 021, W 11:10AM-2:00 PM, CHUNG 125

Section 022, F 5:10-8:00 PM, CHUNG 125

Section 023, W 11:10AM-2:00 PM, CHUNG 128

Teaching Assistants

  • Shaoyi Peng (speng004@ucr.edu), for Section 021 and 023
  • Han Zhou, (hzhou012@ucr.edu), for Section 022

Office Hours: W 2:00pm to 3:00pm, WCH 109

If you have any question regarding lecture and lab, you do not need to send email. Instead, you use github issue section, which can be found at https://github.com/sheldonucr/ucr-eecs168-lab

Reference book

Modern VLSI Design: IP-Based Design by Wayne Wolf, Fourth Edition, Prentice Hall PTR

Grading

Grading for the class will be performed on an individual basis. You will not be competing with the other students for your grade. If all students do well in the class, it is possible everyone will get an A. Your grade is only dependent on the effort you put into the class. Letter grades will be assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an F.

The grading will be based on a weighted sum as follows:

30% Final (will be 40% in lieu of Quizzes).
20% Midterm (one or two midterms)
10% Quizzes (include pop quizzes)
10% Homeworks
30% Lab Assignments

Policies

Punctuality: Please arrive on-time to class. Academic Dishonestly: Any academic dishonesty will no be tolerated. Unless otherwise specifically stated by your instructor or teaching assistant, all course work should be done on your own. Reading: Be prepared. Read over the material being covered in lecture before coming to class. For the most part, the lectures will follow the organization of the book. Any planned deviations from this order will be announced beforehand. Lab Attendance: Lab attendance is mandatory for the entire lab period during which you should be working on course related material. If you finish a lab assignment early, work can always work ahead on the next assignment. Class Mailing List: The class mailing and newsgroup in the ilearn will be used for all course related correspondence such as course announcements. Furthermore, please address all course related questions regarding lectures, homework, labs, etc. to the course mailing list or newsgroup. Cell Phones: Please turn your cell phone off before you come to class.

Lecture Schedule

All the slides will be available after the lecture in ilearn

Subject to change

Lecture Schedule
Week Topic Remark
Week 1 Course Overview, Introduction to VLSI Design, (Chapter 1); Fabrication, Transistor Structures, Basic Transistor Behavior, (Chapter 2); Transistor Characteristics, (Chapter 2). HW1 given after the second lecture. (quiz 1 given in lieu of HW1)
Week 2 Designs Rules and Stick Diagrams, Reliability and Packaging (Chapter 2).  
Week 3 Combinational Logic Functions and CMOS Logic Gates, (Chapter 3); Properties of Combinational Gates, (Chapter 3); Electrical Properties of Combinational Gates (continued), (Chapter 3); HW1 Given after the second lecture. (Quiz 1 in the second lecture)
Week 4 Review of Synopysis Design Tools and Flow (Customer Designer, Design Compiler, IC Compiler etc.). HW2 given after the second lecture.
Week 5 Wire Delay, Buffer Insertion, Etc., (Chapter 3); nMOS Gates, DCVS Logic, Domino Gates, (Chapter 3); Layout, Channel Routing, Simulation, (Chapter 4).  
Week 6 Combinational Network Delay, Logic Optimization (Chapter 4); Transistor Sizing, (Chapter 4); Interconnect Design, Crosstalk, Power Optimization (Chapter 4). HW 3 given in the second lecture. Midterm in second lecture.
Week 7 Review of Verilog hardware design language and digital design method (Chapter 8).  
Week 8 Switch Networks, Combinational Testing, (Chapter 4); Memory Elements, Basics of Sequential Machines, (Chapter 5); Clocking Disciplines, (Chapter 5).  
Week 9 Sequential Machine Design, (Chapter 5); State Assignment, Power Optimization, Design Validation, Sequential Testing, (Chapter 5) HW4 given in second lecture. midterm 2 in first lecture (Tuesday)
Week 10 Shifters, Adders, ALU, (Chapter 6); Multipliers, (Chapter 6); Memories, Datapaths, PLAs, (Chapter 6)  
Final Week Final: Saturday, March 17, 11:00 p.m. - 2:30 p.m. Final in this week.

Homework

Homework assignment 1-4 will be given in ilearn. All the homework will be submitted into ilearn.

Quizzes

We may have one or two quizzes depending on the course progress.

Grading

Grading for the class will be performed on an individual basis. You will not be competing with the other students for your grade. If all students do well in the class, it is possible everyone will get an A. Your grade is only dependent on the effort you put into the class. Letter grades will be assigned using a 10% scale: 90% and above is correspond to an A, 80% and above to a B, 70% and above to a C, 60% and above to a D, and less than 60% to an F. Exams: midterm (two midterms) : 20%


30% Final

20% Midterm

10% Quizzes

10% Homeworks

30% Lab Assignments


All of them will be graded on the scale of 0 to 100 with 100 being the maximum score.

Lab Schedule

Every communication (Please don't use email regarding lab question) will be at https://github.com/sheldonucr/ucr-eecs168-lab/issues. Please use GITHUB page instead of email to ask any question to TA.

For the lab schedule, more detail can be found at https://github.com/sheldonucr/ucr-eecs168-lab

Late assignment submission policy

You are only allowed two late submissions in this class.

For each late submission, you are only allowed only two late days with discounted credits for the assignment you are late.

  • Late by first day: take 20% off the total credit of the assignment
  • Late by second day: take 40% off the total credit of the assignment
  • Late by third day and thereafter: not allowed.