EE/CS 120A Spring 2018: Introduction to Logic Design
Overview
Catalog description :
Course Objectives :
Basic information
Labs:
Labs:
Teaching Assistants: Hyunjong Choi
Section 021 and 022: Hyunjong Choi (hchoi036@ucr.edu): Time: 2:00pm to 4:00pm (TR) in Lab room or Eng-II 109
Please buy the book at UCR book store (ISBN 978-0-470-53108-2)
The discounted version is also available directly from the publisher Digital Design 2nd Edition Binder Ready Version
- Lecture component (60 points + 3 bonus points)
- 20 pts: Midterm
- 24 pts: Final
- 16 pts: Homeworks -- 8 @ 2 pts
- 3 pts: in lecture pop quizes (bonus points)
- Lab component (40 points)
- 30 pts: Lab assignments (5 for lab 1-6)
- 10 pts: The mini project
Grades will be assigned using a conventional grading scale: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F. +/- grades will be given. Students are NOT competing against one another, but rather against the scale -- all students can get good grades if all do well. We may adjust ("curve") an individual assessment item if such adjusting HELPS the class.
Minimum competency requirement: We want students to master both the conceptual as well as the hands-on aspects of the course. Thus, students must receive a passing grade (60% or better) in each of the lecture component and lab component, in order to receive a passing course grade (D- or better).
Study groups:
Enrolling in this course gives you automatic access to the UCR "ilearn" site Your login id is the name field of your ucr student email address (name@student,ucr,edu), and your initial password is your Student ID (no dashes or spaces). Most students will be automatically subscribed to the mailing list in ilearn when enrolled in the course. If you are UCR extension students, please contact the instructor to add you into the this course via ilearn.
Lecture Schedule
Read the book before lecture! Reading ahead is one of the most effective ways of doing better in class -- you'll be amazed how much more useful the lectures will be. We'll follow the book closely.
Also for students who can't access ilearn, please let me know so that I can enroll you into ilearn for this course
- Week 1:
- Ch1 -- Introduction: digital systems, number systems, microprocessors versus custom designs.
- Ch2 -- Combinational logic design: gates, Boolean algebra.
- Homework 1
- Week 2:
- Ch2: Combinational logic design: combinational design process, more gates, mux, decoders.
- Verilog introduction: combinational logic
- Homework 2
- Week 3:
- Ch6: Combinational logic optimization: K-maps.
- Ch3: Sequential logic design: latch, flip-flop.
- Homework 3;
- Week 4:
- Ch3: Sequential logic design: finite stat machines, controller design.
- Verilog introduction: sequential logic
- Midterm 1 (in friday lecture time)
- Week 5:
- Ch6: Sequential logic optimization: state reduction, state encoding.
- Ch4: Datapath components: registers.
- Homework 4
- Week 6:
- Ch4: Datapath components: adders, comparators.
- Verilog introduction: datapath
- Homework 5
- Week 7:
- Ch4: Datapath components: multipliers, subtractors, ALU, counters, timers, shifters, register files.
- Homework 6; midterm 2 (tenative)
- Week 8:
- Ch5: High-level state machines, RTL design process.
- Verilog introduction: RTL
- Homework 7
- Week 9:
- Ch5: More RTL design, memory components.
- Ch5: Queue, design hierarchy
- Homework 8
- Week 10:
- Ch7: Programming IC technologies.
- Review
- Final exam: Monday, June 11, 3:00 p.m. - 6:00 p.m. (same room as lecture).
Lab schedule
Read the lab overview and report format.
- Week 1: No Lab
- Week 2: Lab 1 -- Xilinx Enviroment
- Week 3: Lab 2 -- Decoders and Muxes
- Week 4: Lab 3 -- Programming Combinational Logic on Basys FPGA Board
- Week 5: Lab 4 -- Sequential Logic Design
- Week 6: Lab 5 -- Datapath Components - Adders
- Week 7: Lab 6 -- Timer Design
- Week 8: Mini Project
- Week 9: Mini Project
Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C
General course features and policies (please read these carefully)
- Material covered: You'll be responsible for learning material covered in lecture, in the textbook, and in lab. We expect you to read the textbook; lecture only emphasizes key material, but does not cover all required material alone.
- Collaboration policy (TA/instructor may override for particular assignment):
- Midterm, final, quizzes, lab practical -- Obviously no collaboration
- In-lecture exercises -- Dependent on instructor instructions for particular exercise.
- Homeworks -- Collaboration strongly ENCOURAGED. Study groups are great. You should still do your own solution, and should not turn in *identical* solutions as others, but similar solutions are O.K. Remember though -- these are designed to help you on the assesment items, so relying too heavily on others will hurt you during assessment.
- Lab assignments -- Limited collaboration may be acceptable, but submissions must represent YOUR OWN original work. Sharing code or team-coding are not allowed. Copying code from ANY source (any book, current or past students, past solutions, etc.) is not allowed. Collaboration may consist of discussing the general approach to solving the problem, but should not involve communicating in code or even pseudo-code. Students may help others find bugs. Your code must be unique -- the odds of randomly obtained highly-similar code is very low. Design, like surgery or driving a car or playing golf, can only be learned by doing it yourself!
- Academic dishonesty: cheating is strongly punished. Report cheating (anonymously if you wish) at: https://www.cs.ucr.edu/cheating/. Note: In some courses, we use a powerful commercial tool that automatically compares all programs (this quarter and from past quarters too), neglecting changes in variable names, spacing, etc., and detects copied code. We regularly catch several cases of copying in this course EVERY QUARTER. PLEASE, don't risk it!! A couple more notes. Be aware that a subset of exams may be photocopied, for comparison with exams submitted for regrades. Also, be aware that lying to an instructor in order to be able to make up a missed exam or in other ways to obtain a better grade can be treated as academic dishonesty. During exams, cell phones must be stored away in a place not visible (e.g., inside a backpack).
- Regrade policy: regrade requests must be submitted in writing and within one week of the distribution of the graded material. Grade-database errors should also be pointed out within one week of posting.
- Communicating with the instructors and TAs: when sending electronic mail to the instructors or TAs, please remember that many students have the same name, and your instructor may be teaching other courses too. So please give your full name and list the course you are referring to, and preferably include your student ID number. We prefer that you use your UCR email account so that you get used to it (remember that UCR sends many official notices now only by email). Please try to be polite and professional, and use reasonable grammar and formatting.
- Cell phones: During lectures and lab sessions, please turn off your cell phone.
- Lab attendance: is required for the full 3-hour lab. If you finish early, work ahead on labs, do homework, read ahead, and help others if allowed (teaching increases your own learning).
- Lab enrollment : To reduce disruptions and provide for the best educational environment, all persons in lab during scheduled lab time should be formally registered in that section. In general, no swapping sections and no unregistered people in the lab are allowed, even if there are extra computers.
- Homeworks and lab reports: Homeworks are due at the beginning of the class period on the due date. Lab reports are due at the beginning of the lab period on the due date. No late homeworks are accepted. Your work must be completely typeset with a word processor. Circuit diagrams can be drawn using any drawing program or by hand, but it must be very neat. Handwritten works will NOT be accepted. Lab reports must follow this format.
- Late/early policy for lab assignments:
- Late penalty for lab assignments due before the midterm: 7% for 1-day late, 14% for 2-days, not accepted thereafter.
- Late penalty for lab assignments due after the midterm: 10% for 1-day late, 20% for 2-days, not accepted thereafter.
- BONUS for any lab assignment turned in EARLY: 2% for 1-day early, 4% for 2-days early, 6% for 3-days or more early.
- "Day early/late" is defined as 24 hours before/after the due time.
- Time Requirements: This is a five-unit engineering course. As such, you should expect to spend 3 hours/week in lecture, 6 hours/week in lab, and 6 to 10 hours/week doing individual study (readings, homeworks, programming, lab preparation, etc) -- no exaggerating here! Please don't underestimate the time you will need to spend on this course. These are real time amounts spent by successful past students. Engineering and CS are challenging disciplines requiring extensive time to master -- it's worth it in the end (great jobs, great pay, respect, etc.), but those things don't come for free. So practice, practice, practice! Work hard in school, then reap the rewards of a great career.
- Final grades: Per university policy, changes to your final grade will be made only in the event of a clerical error. Asking your instructor how far you were from a cutoff and what extra work you can do to improve the grade is not appropriate.