Chase is a PhD candidate who joined the VSCLab in 2015. His research includes topics in the areas of Simulation and Design Automation with applications in reliability and hardware security. He has worked on projects including simulation of Electromigration effects in VLSI circuits, the design of reliability based hardware Trojans and detection of counterfeit ICs, applications and acceleration of Ising models for graph partitioning, and system level simulations and optimization of core DVFS policies in many-core CPUs.
In addition to his research, Chase has worked as the instructor for EE/CS120A: Introduction to Logic Design.
Chase has participated in several industry internships. At Cadence Design Systems (2017) he worked on Big Data storage and visualization. At Intel Corporation (2018, 2019) he works to develop Signal Integrity simulation tools.