VLSI System and Computation Lab

WE ENGINEER EXCELLENCE

Compact Modeling, Reduction and Simulation of Interconnect Parasitic Circuits

August 01, 2008

Principle Investigator

Dr. Sheldon Tan (PI)

 

Graduate Students:

  • Hai Wang,
  • Boyuan Yan,
  • Duo Li,
  • Pu Liu

 

Funding supports

We appreciate the following funding agencies for their generous supports of this project.
  • National Science Foundation, "CAREER: Career Development Plan: Behavioral Modeling, Simulation and Optimization for Mixed-Signal System in a Chip", (CCF-0448534, CCF-0529754 and CCF-0731962, CCF- 0830304, for REU supplements), 6/1/2005-5/31/2011. PI: Sheldon Tan.
  • UC MICRO Program (via Cadence Design Systems Inc.) (#05-111), "Combined Multi-Input Multi-Output Model Order Reduction and Topology Reduction for High-Performance VLSI Systems", Sept. 2005 to Aug. 2006, PI: Sheldon Tan
  • UC MICRO Program (via Intel Corporation) (#07-105), "Compact Modeling Techniques for Inductively Coupled Interconnect Circuits", Sept. 2007 to Aug. 2008, PI: Sheldon Tan

Project Descriptions

As VLSI technology advances into the sub-100nm regime with increased operating frequency and decreased feature sizes, the nature of the VLSI design has changed significantly. One fundamental paradigm change is that parasitic interconnect effects dominate both the chip's performance and the design's complexity growth. Management of the design parasitic by circuit reduction techniques becomes impressive.

In this project, we investigate the compact modeling techniques of on-chip interconnects and general linear time invariant systems (LTI) because interconnect parasitics, which are modeled as linear RLCM circuits, are the dominant factors for complexity growth. Unchecked parasitics from on-chip interconnects and off-chip packaging will de-tune the performance of high-speed circuits in terms of slew rate, phase margin and bandwidth. Reduction of design complexity especially for the extracted high-order RLCM networks is crucial for reducing the explosive design productivity gap in the nanometer VLSI design and verification.

The PI and MSLAB at UC Riverside have many a number of contributions to this field in the past. In 2003, the PI proposed a new hierarchical model order reduction technique based on the Determinant Decision Diagram (DDD) symbolic analysis[J1]. The idea is to perform the hierarchical symbolic analysis (assume frequency variable s is the only parameter) and drive the truncated transfer functions. The approach was shown to be more accurate than Krylov subspace methods. The new method can be viewed as a general Y-Delta reduction approach[B1] and have been used for RF spiral inductor modelings[J2].

Although many progresses have been made in this field in the past two decades, there are still many outstanding problems yet to be solved. Among them are (1) reduction of interconnect circuits with massive ports, which are very common in practical VLSI systems (like memory, DSP ICs); (2) wideband reduction of parasitic circuits for analog/mixed-signal/RF/millimeter circuits, where accuracy is required for the wide frequency bandwidth, (3) passive reduction of linear dynamic systems with different input and outputs, which can’t be solved by existing projection based framework, (4) Efficient variational or statistical reduction techniques consider process variations (5) reduction technique for general nonlinear circuits.

 

Invited Presentations

  • Dr. Sheldon Tan, Tsinghua University, Beijing, China, “Modeling and Simulation of Nanometer Interconnect Circuits”, Aug. 23, 2005.
  • Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, “Passive model order reduction and terminal reduction for interconnect circuits with multiple terminals”, Nov. 9, 2005.
  • Dr. Sheldon Tan, University of Tokyo, Tokyo, Japan, “Hierarchical model order reduction for wideband interconnect modeling”, Jan. 25, 2006.
  • Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, “TermMerg: Fast terminal reduction for interconnect circuits with multiple terminals”, Feb. 7, 2006.
  • Dr. Sheldon Tan, Cadence Design Systems, Inc., San Jose, CA, "An extended SVD-based terminal and model order reduction algorithm"€, June 12, 2006.
  • Dr. Sheldon Tan, System LSI Design Workshop, Fukuoka, Japan, "Recent Advance in Terminal and Model Order Reduction for Interconnect Circuits"€, Sept. 9, 2006.
  • Dr. Sheldon Tan, Electrical Engineering Colloquium, UCR, "Modeling and Simulation of Sub-90nm Interconnect Circuits: Problem, Solution and Future Challenges"€, May 7, 2007.
  • Dr. Sheldon Tan, Beijing JiaoTong University, Beijing, China, "€œModeling and analysis of 90nm VLSI Interconnects: problem, solutions and future challenges"€, July 5, 2007.
  • Dr. Sheldon Tan, Tsinghua University, Beijing, China, "€œPassive compact modeling of inductively coupled interconnect circuits by projection-based balanced truncation"€, July 20, 2007.
  • Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Numerical solution of eigenvalue problems and singular value decomposition (SVD)"€, March 21, 2008.
  • Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "Partitioning-based reduction method for large linear network analysis"€, June 18, 2008.
  • Dr. Shedlon Tan, Workshop of SoC Design Methodologies, National Tsing-Hua Univ., Tsin-Chu, Taiwan, "€œEfficient reduction-based methods for on-chip power grid network analysis"€, Sept. 9, 2008.
  • Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "€œHierarchical Reduction Based Analyses Method For Large Power Delivery Networks"€, Oct. 9, 2008.
  • Dr. Sheldon Tan, International Conference on Solid-State and Integrated Circuit Technology (ICSICT'08), Beijing, "€œA Survey of RLCK Reduction and Simulation Methods by Fast Truncated Balanced Realization"€, Oct. 21, 2008.
  • Dr. Sheldon Tan, Rice University, ECE Department, TX, "€œDecentralized Model Order Reduction and Simulation of Linear Networks with Massive Ports", Jan. 29, 2009.
  • Dr. Sheldon Tan, Cadence Design Systems Inc, San Jose, CA, "€œPerformance Comparison for Reduction-Based P/G Network Analysis Methods"€, Feb 26, 2009.
  • Dr. Sheldon Tan, VirageLogic Corporation, Fremont, CA, "Boost Post-layout Verification Efficiency by Circuit Complexity Reduction"€, May 5, 2009.
  • Dr. Sheldon Tan, CEC Huada Electronic Design Co., Ltd, Beijing, China, “Boost Post-layout Verification Efficiency for Analog Circuits by Compact Modeling of Parasitics”, July 24, 2009.

 

Software package releases

The UiMOR program: UC Riverside Model Order Reduction Suite Tool, which can perform wideband complexity reduction and generate SPICE-compatible netlists. Relevant Publications

 

Relevant publications

Books

  • B1. Zhanhai Qin, Sheldon X.-D. Tan and Chung-Kuan Cheng, Symbolic Analysis and Reduction of VLSI Circuits, Springer Publisher, 2005, ISBN: 0-387-23904-9; e-ISBN: 0-387-23905-7.
  • B2. Sheldon X.-D. Tan and Lei He, Advanced Model Order Reduction Techniques for VLSI Designs, Cambridge University Press, 2007, ISBN-13 978-0-521-86581-4, ISBN-10 0-521-86581.

 

Journal publications

  • J1. S. X.-D. Tan, "A general hierarchical circuit modeling and simulation algorithm"€, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 418-434, March 2005.
  • J2. Z. Qi,, H. Yu, P. Liu, S. X.-D. Tan, L. He, "€œWideband passive multi-port model order reduction and realization of RLCM circuits"€, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol. 25, No. 8, pp. 1496-1509, Aug. 2006.
  • J3. P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy, "€œAn efficient terminal and model order reduction algorithm", Integration, the VLSI Journal, vol.41, no.2, pp.210-218, Feb. 2008. (online permanent DOI link)
  • J4. B. Yan, S. X.-D. Tan, B. McGaughy, "Second-order balanced truncation for passive-order reduction of RLCK circuits"€, IEEE Transaction on Circuit and System II (TCAS-II), vol. 55 no. 9, pp. 942-946, Sept 2008.
  • J5. N. Mi, B. Yan, S. X.-D. Tan, "€œMultiple block structure-preserving reduced order modeling of interconnect circuits"€, Integration, The VLSI Journal, vol. 42, no. 2, pp.158-168, 2009, (online permanent DOI link)
  • J6. D. Li, S. X.-D. Tan, L. Wu, "Hierarchical Krylov subspace based reduction of large interconnects", Integration, The VLSI Journal, vol. 42, no.2, pp193-202, 2009. (online permanent DOI link)
  • J7. H. Yu, C. Chu, Y. Shi, D. Smart, L. He and S. X.-D. Tan, "€œFast analysis of large scale inductive interconnect by block structure preserved macromodeling"€, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press).
  • J8. D. Li, S. X.-D. Tan, "€œFast analysis of on-chip power grid circuits by extended truncated balanced realization method"€, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E92-A, no. 12, pp.3061-3069, 2009.
  • J9. S. X.-D. Tan, B. Yan and H. Wang, "€œRecent advance in non-Krylov subspace model order reduction of interconnect circuits"€, Tsinghua Science and Technology, (in press) (invited)
  • J10. B. Yan, S. X.-D. Tan and J. Fan, "€Passive rational interpolation based reduction via Caratheodory extension for general systems"€, IEEE Transaction on Circuit and System II (TCAS-II), (in press).

Conference publications

  • C1 S. X.-D. Tan, "A general s-domain hierarchical network reduction algorithm", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), San Jose, CA, pp. 650-657, Nov. 2003.
  • C2 H. Yu, L. He and S. X.-D. Tan, "Compact macro-modeling for on-chip RF passive components", Proc. IEEE International Conference on Communications, Circuits and Systems, Chengdu, vol. 2, pp. 199-202, China, 2004 .
  • C3 Z. Qi , S. X-.D. Tan, H. Yu , L. He and P. Liu, œ"Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'™05), pp.224-229. Shanghai, China, Jan. 2005.
  • C4 H. Yu, Z. Qi, L. He and S. X.-D. Tan, "A wideband hierarchical circuit reduction for massively coupled interconnects", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'™05), pp.111-114, Shanghai, China, Jan. 2005.
  • C5 P. Liu, Z. Qi and S. X.-D. Tan, "Passive hierarchical model order reduction and realization of RLCM circuits", Proc. Int. Symposium. on Quality Electronic Design (ISQED'05), pp. 603-608, San Jose, CA, March 2005.
  • C6 P. Liu, Z. Qi, A. Aviles, S. X.-D. Tan, "A general method for multi-port active network reduction and realization", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.7-12, San Jose, CA, Sept., 2005.
  • C7 H. Yu, L. He, S. X.-D. Tan, œ"Block structure preserving model reduction", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.1-6, San Jose, CA, Sept., 2005.
  • C8 P. Liu, S. X.-D. Tan, H. Li, Z. Qi, J. Kong, B. McGaughy, L. He, "An efficient method for terminal reduction of interconnect circuits considering delay variations", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD), pp. 821-826, San Jose, CA, Nov. 2005.
  • C9 P. Liu, S. X.-D. Tan, B. McGaughy, L. Wu, "Compact reduced order modeling for multiple-port interconnects", Proc. Int. Symposium. on Quality Electronic Design (ISQED'06), pp.413-418, San Jose, CA, March 2006.
  • C10 P. Liu, S. X.-D. Tan, B. Yan, B. McGaughy "œAn extended SVD-based terminal and model order reduction algorithm", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.44-49, San Jose, CA, Sept., 2006.
  • C11 J. Fan, N. Mi, S. X.-D. Tan, "Variational compact modeling and simulation for linear dynamic systems", IEEE International Workshop on Behavioral Modeling and Simulation (BMAS), pp.17-22, San Jose, CA, Sept., 2006.
  • C12 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, "Passive interconnect macromodeling via balanced truncation of linear systems in descriptor form", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'07), pp. 355-360, Yokohama City, Japan, Jan. 2007.
  • C13 B. Yan, P. Liu, S. X.-D. Tan, B. McGaughy, "Passive modeling of interconnects by waveform shaping", Proc. Int. Symposium. on Quality Electronic Design (ISQED'™07), pp.356-361, San Jose, CA, March 2007.
  • C14 N. Mi, B. Yan, S. X.-D. Tan, J. Fan, H. Yu "General block structure-preserving reduced order modeling of linear dynamic circuits", Proc. Int. Symposium. on Quality Electronic Design (ISQED'™07), pp. 633-638, San Jose, CA, March 2007.
  • C15 J. Fan, N. Mi, S. X.-D. Tan, Y. Cai and X. Hong, "Statistical model order reduction for interconnect circuits considering spatial correlations", Proc. Design, Automation and Test in Europe (DATE'07), pp. 1508-1513, Nice, France, April 2007.
  • C16 B. Yan, S. X-.D. Tan, P. Liu, B. McGaughy, "SBPOR: second-order balanced truncation for passive model order reduction of RLC circuits", Proc. IEEE/ACM Design Automation Conference (DAC'07), pp.158-161, San Diego, CA, 2007.
  • C17 D. Li, S. X.-D. Tan, "œHierarchical Krylov subspace reduced order modeling of large RLC circuits", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'08), pp.170-175, Seoul, Korea, Jan. 2008.
  • C18 D. Li, S.X.-D. Tan, B. McGaughy, "ETBR: Extended truncated balanced realization method for on-chip power grid network analysis", Proc. Design, Automation and Test in Europe (DATE'08), pp.432-437, Munich, Germany, March 2008.
  • C19 B. Yan, L. Zhou, S. X.-D. Tan, J. Chen, B. McGaughy, "œDeMOR: Decentralized model order reduction of linear networks with massive ports", Proc. IEEE/ACM Design Automation Conference (DAC'08), pp. 409-414, Anaheim, CA, 2008.
  • C20 B. Yan, H. Wang, S. X.-D. Tan, "Survey of RLCK reduction and simulation methods by fast truncated balanced realization", Int, Conf. Solid State and Integrated Circuit Technology (ICSICT'08), pp. H1.3, Beijing, China, Oct. 2008. (invited)
  • C21 H. Yu, X. Liu, H. Wang, S. X.-D. Tan, "Fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp.211-216, Taipei, Taiwan, Jan. 2010.
  • C22 H. Wang, S. X.-D. Tan, G. Chen, "œWideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp.31-26, Taipei, Taiwan, Jan. 2010.
  • C23 B. Yan and S. X.-D. Tan, G. Chen, Y. Cai, "Model reduction of interconnects via double gramians approximation", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'10), pp. 25-30, Taipei, Taiwan, Jan. 2010.
Tags
More Project