VLSI System and Computation Lab

WE ENGINEER EXCELLENCE

VLSI reliability, resilience, fault-tolerant computing and dynamic reliability management

September 01, 2019

Principle Investigators

Graduate Students

Current Students

  • Sheriff Sadiqbatcha 
  • Shuyuan Yu
  • Wentian Jin
  • Jinwei Zhang
  • Mohammadamir Kavousi
  • Yibo Liu
  • Liang Chen (post-doc, SJTU)
  • Subed Lamichlane 
  • Jincong Lu

Graduate Students (graduated)

  • Han Zhou (First job: Synopsys)
  • Shaoyi Peng (First job: Carabras Systems)
  • Zeyu Sun (First job: Cadence)
  • Chase Cook (First job: Intel Corp)
  • Dr. Henyang Zhao (First job: Google)
  • Dr. Xin Huang (First job: Airbnb)
  • Dr. Taeyoung Kim (First job: Intel Corp)
  • Dr. Kai He (First job: Cadence)

Industry Liaisons

  1. Dr. Mehul Shroff, NXP Semiconductor, Inc.
  2. Dr. Ertugrul Demircan, NXP Semiconductor, Inc.
  3. Dr. Ashish X. Gupta, Intel Corporation
  4. Dr. Jinjun Xiong, IBM Research

Academic Collaborators

  • Dr. Haibao Chen, Shanghai Jiaotong University, Shanghai, China

Funding

We appreciate the following funding agencies for their generous supports of this project.

  1. National Science Foundation CISE CCF Core Small program (CCF-1816361), “SHF: Small:  Machine Learning Approach for Fast  Electromigration Analysis and Full-Chip Assessment, $500,000,  Oct. 1st, 2020  to Sept 30th, 2023, single PI.
  2. National Science Foundation, Office of International Science and Engineering (OISE): (OISE-1854276),  “ IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design”, $300K, April 1, 2019 to March 29, 2022, Single PI.
  3. National Science Foundation, Office of International Science and Engineering (OISE): (OISE-1854276),  “ IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design”, $300K, April 1, 2019 to March 29, 2022, Single PI.
  4. National Science Foundation CISE CCF Core Small program (CCF-1816361), "€œEM-Aware Physical Design and Run-Time Optimization for sub-10nm 2D and 3D Integrated Circuits"€, $450,000, August 1st, 2018 to July 31th 2021, single PI.
  5. Defense Advanced Research Projects Agency (DARPA) (HR0011-16-2-0009), "Advanced Modeling and Analysis for Accelerating Effects of Electromigration and Stress Migration for Copper Interconnects of ICs", $462,644, Feb. 2016-Aug, 2018 (30 months). Single PI.
  6. National Science Foundation CISE CCF Core Small program (CCF-1527324), "SHF:Small: Physics-Based Electromigration Assessment and Validation For Reliability-Aware Design and Management", $450,000, June 1st, 2015 to May 31th 2019, single PI.
  7. National Science Foundation, NSF FRS (Failure Resistant Systems) program (CCF-1255899), "Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors", $180K, April 1, 2013 to March. 31, 2016. PI (single PI).
  8. Semiconductor Research Corporation, NSF/SRC Multi-core Program (SRC 2013-TJ-2417), "Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors", $120K, April 1st, 2013 to Match 30, 2016, PI.

Awards

  • The honorable mention Best Paper Award, "Accelerating electromigration wear-out effects based on configurable sink-structured wires”, 15th International conf. on Synthesis, modeling, analysis and simulation methods and applications to circuit design (SMACD18), Prague, July, 2018.
  • J. Peng, H. Chen, H. Zhao, Z. Sun and S. X.-D. Tan, "Dynamic temperature-aware reliability modeling for multi-branch interconnect trees", in Proc. International Conference on ASIC (ASICON17), Guiyang, China, Oct. 2017. (Best Paper Award).
  • Dr. Ertugrul Demircan and Dr. Mehul Shroff received the 2017 SRC Mahboob Khan Outstanding Industry Liaison/Associate Awards with collaboration of VSCLab.
  • Dr. Valeriy Sukharev received the prestigious SRC Mahboob Khan Outstanding Industry Liaison Award!
  • Mahboob Khan Outstanding Industry Liaison/Associate Awards recognizes those individuals who demonstrate outstanding commitment and effectiveness in facilitation of university research, mentoring of graduate students, and dissemination of knowledge and research results to industry. Dr. Sukharev has been selected as a recipient of one of the 2014 Mahboob Khan Outstanding Industry Liaison/Associate Awards. His dedication and personal contributions as a liaison to SRC research programs under the direction of Dr. Sheldon Tan, University of California Riverside on SRC research #2417.001 - Thermal-Sensitive System-Level Reliability Analysis and Management for Multi-Core and 3D Microprocessors has served to strengthen our industry. SRC laud his efforts and hold his accomplishments as a role model for others. The Mahboob Khan Outstanding Industry Liaison/Associate Awards will be presented at the SRC TECHCON 2014 banquet on Monday, September 8th in Austin, TX.
  • X. Huang, T. Yu, V. Sukharev, S. X.-D. Tan, "Physics-based electromigration assessment for power grid networks", Proc. IEEE/ACM Design Automation Conference (DAC'14), San Francisco, June, 2014. (Best Paper Award Nomination (12 out of 787 submissions, 1.5%))
  • H. Chen, S. X.-D. Tan, X. Huang, V. Sukharev, "New electromigration modeling and analysis considering time-varying temperature and current densities", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'15), Chiba, Japan, Jan. 2015. .(Best Paper Award Nomination)

Project Descriptions

Background

Reliability is becoming a limiting constraint in high-performance nanometer VLSI chip designs due to the high failure rates in deep submicron and nanoscale devices. It was expected that the future chips will show sign of reliability-induced age much faster than the previous generations. Among of many reliability effects, electromigration (EM)-induced reliability has become a major design constraint due to aggressive transistor scaling and increasing power density.

Electromigration (EM) is a physical phenomenon of the oriented migration of metal (Cu) atoms along a direction of applied electrical field due to the momentum exchange between atoms and the conducting electrons. Migration of atoms results in metal density depletion or accumulation, which leads to build-up of hydrostatic stresses across the conductor. EM can degrade both global interconnects such as power grid networks and signal wires when the current densities are sufficiently high (about 1MA/cm^2). However, the power grid networks are more susceptible to EM effects due to the conduction of unidirectional currents.

The research motivation and goals

The objective of this project is develop physics-based predictable EM models for general multi-branch interconnect trees and structures which can consider varying current and temperature (temperature migration) stressing for both normal and stream stressing conditions. The second goal of this project is to develop novel, efficient system and architecture level reliability analysis and optimization techniques for multi-core and 3D microprocessors. We seek to regulate on-chip temperature, which affect the wear-out faults the most, to manage the system reliability dynamically.

Specifically this project aims to develop physics-based predictable EM models for general multi-branch interconnect trees and structures and the design time and run-time long-term reliability optimization and management methods at circuit and system levels.   The new physics-based EM models and full-chip assessment techniques can perform model validation for accurate, yet efficient EM sign-off analysis at design stage and EM-aware reliability management at run time for nanometer VLSI chips. 

We expect the following results coming from this research:

  1. Development of physics-based EM models and fast EM signoff for general multi-branch interconnects
  2. Development of dynamic EM models, which can consider the varying current and temperatures
  3. Development of reliability-aware dynamic thermal management techniques for the multi-core and 3D stacking microprocessors.
  4. Design full-chip thermal estimation and prediction techniques considering practical limited thermal sensors, noise errors, for run-time thermal management and optimization.
  5. Development of EM-aware physical layout optimization techniques and EM lifetime optimization for TSV-based 3D chips
  6. Development of fast EM wearout acceleration techniques based on reservoir and sink based multi-segment interconnect structures.
  7. Will explore the run-time recovery effects of the EM aging and wear-out effect to extend the EM lifetime of the signal and power/ground (P/G) networks for 3D stacked ICs.
  8. Develop new machine learning based dynamic thermal/power/reliability management and optimization techniques for embedded and high performance microprocessors.

Features of the proposed methods

  1. Address the long-term thermal-sensitive reliability issues such EM, SM, TDDB, thermal cycling effects by system level thermal and power management.
  2. New fast physics-based EM assessment techniques which is more accurate and predictable than existing Black and Blech's equations.
  3. New physics-based topology-aware EM models can be easily used with physical design tools for EM-aware physical design and optimization.
  4. The new EM and SM (stress migration) models can be used for both normal chip operations and extreme stressing conditions.

Software Download

The developed EM models in matlab codes are shared at  github:  physics-based EM assessment analysis codes and documents

The latest devoted full-chip could EM and IR analysis tool, EMSpice, which can be download at Github: EMspice tool 

Publications

Journal publications

  • J1 D. Li, S. X.-D. Tan, E. H. Pacheco, M. Tirumala, "Parameterized architecture-level thermal modeling for multi-core microprocessors", "ACM Transaction on Design Automation of Electronic Systems" (TODAES), vol. 15, no. 2, pp.1-22, February 2010 (one of top 10 downloaded ACM TODAES Articles published in 2010).
  • J2 T. Eguia, S. X.-D. Tan, R. Shen, D. Li, E. H. Pacheco, M. Tirumala, L. Wang, "General parameterized thermal modeling for high-performance microprocessor design", "IEEE Transactions on Very Large Scale Integrated Systems" (TVLSI), Vol. 20, No. 2, pp.221-224, Feb. 2012. 10.1109/TVLSI.2010.2098054.
  • J3 H. Wang, S. X.-D. Tan, D. Li, A. Gupta, Y. Yuan, "Composable Thermal Modeling and Simulation for Architecture-Level Thermal Designs of Multi-core Microprocessors", "ACM Transactions on Design Automation of Electronic Systems" (TODAES), vol. 18, no. 2, March 2013.
  • J5 Z. Liu, S. X.-D. Tan, X. Huang and H. Wang, "Task migrations for distributed thermal management considering transient effects," IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 23, no. 2, Feb. 2015.
  • J6 Z. Liu, S. Swarup, S. X.-D. Tan, H. Chen, H. Wang, "Compact lateral thermal resistance model of TSVs for fast finite-difference based thermal analysis of 3D stacked ICs", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 10. Oct. 2014.
  • J7 H. Chen, S. X-.D. Tan, D. H. Shin, X. Huang, H. Wang and G. Shi, "H2-Matrix-based Finite Element Linear Solver for Fast Transient Thermal Analysis of High-Performance ICs", Int. J. Circ. Theor. Appl. (in press), DOI: 10.1002/cta.2051.
  • J8 H. Chen, Y. Li, S. X.-D. Tan, X. Huang, H. Wang and N. Wong, "H-matrix based finite-element-based thermal analysis for 3D ICs", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 47, pp. 47:1-25, 2015.
  • J10 X. Huang, A. Kteyan, S. X.-D. Tan, V. Sukharev, "Physics-based electromigration models and full-chip assessment for power grid networks", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 11, pp.1848-1861, Nov. 2016.
  • J11 H. Chen, S. X.-D. Tan, X. Huang, T. Kim, V. Sukharev, "Analytical modeling and characterization of electromigration effects for multi-branch interconnect trees", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 11, pp.1811-1824, Nov. 2016.
  • J12 H. Wang, J. Ma, S. X.-D. Tan, C. Zhang, H. Tang, and K. Huang, "Hierarchical dynamic thermal management method for high-performance many-core microprocessors", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol 22, No.1, 1:1-1:21, July 2016.
  • J13 X. Huang, V. Sukharev, J.-H. Choy, M. Chew, T. Kim, S. X.-D. Tan, "Electromigration assessment for power grid networks considering temperature and thermal stress effects", Integration, The VLSI Journal, , Volume 55, September 2016, Pages 307-315, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2016.04.001.
  • J14 K. He, X. Huang, S. X.-D. Tan, "EM-based on-chip aging sensor for detection of recycled ICs", IEEE Design & Test, pp.56-64, June, 2016.
  • J15 X. Huang, V. Sukharev, T. Kim, S. X.-D. Tan, "Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing," Integration, the VLSI Journal, Available online 12 November 2016, ISSN 0167-9260, https://doi.org/10.1016/j.vlsi.2016.10.007.
  • J 16 T. Kim, Z. Sun, H.-B. Chen, H. Wang, S. X.-D. Tan, "Energy and lifetime optimizations for dark silicon manycore microprocessor considering both hard and soft errors", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), Vol. 25, No. 9, pp. 2561-2574, Sept. 2017
  • J17 H.-B. Chen, S. X.-D. Tan, J. Peng, T. Kim, J. Chen, "Analytical modeling of electromigration failure for VLSI interconnect tree considering temperature and segment length effects", IEEE Transaction on Device and Materials Reliability (T-DMR), (in press).
  • J18 S. X.-D. Tan, H. Amrouch, T. Kim, Z. Sun, C. Cook, J. Henkel, "Recent advances in EM and BTI induced reliability modeling, analysis and optimization", Integration, The VLSI Journal, (https://doi.org/10.1016/j.vlsi.2017.08.009), (invited)
  • J19 S. Peng, H. Zhou, T. Kim, H.-B. Chen, S. X.-D. Tan, "Physics-based compact TDDB models for low-k BEOL copper Interconnects with time-varying voltage stressing", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), (in press).
  • S. Wang, T. Kim, Z. Sun, S. X.-D. Tan, M. Tahoori, “Recovery-aware proactive TSV repair for electromigration lifetime enhancement in 3D ICs”, IEEE Transactions on Very Large Scale Integrated Systems  (TVLSI),  Vol. 26, no. 3, pp. 531-543, March 2018. DOI: 10.1109/TVLSI.2017.2775586
  • Z. Sun, E. Demircan, M. Shroff,  C. Cook, S. X.-D. Tan, “Fast electromigration immortality analysis for multi-segment copper interconnect wires”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  vol. 37, no. 12, pp. 3137-3150, Dec. 2018.  10.1109/TCAD.2018.2801221
  • C. Cook, Z. Sun, E. Demircan, M. Shroff,  S. X-.D. Tan, “Fast electromigration stress evolution analysis for interconnect trees using Krylov subspace method”, IEEE Transactions on Very Large Scale Integrated Systems  (TVLSI),  Vol. 26, no. 5, pp. 969-980, May 2018.

  • J23 T. Kim, Z. Liu, S. X.-D. Tan, "Dynamic reliability management based on resource-based EM modeling for multi-core microprocessors", Microelectronics Journal, vol. 74, pp. 106-115, April 2018.

  • J24 T. Kim, S. X.-D. Tan, C. Cook and Z. Sun,  "Detection of counterfeited ICs via on-chip sensor and post-fabrication authentication policy"€, Integration, The VLSI Journal, vol.63, pp 31-40, 2018 http://authors.elsevier.com/sd/article/S0167926017306399. DOI: 10.1016/j.vlsi.2018.05.002

  • J25 H. Zhao and S. X.-D. Tan, "œPostvoiding FEM analysis for electromigration failure characterization", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), DOI: 10.1109/TVLSI.2018.2861358, Vol. 26, No. 11, pp. 2483-2493, Nov. 2018.

  • J26 H. Zhou, Z. Sun, S. Sadiqbatcha, N. Chang and S. X.-D. Tan, "EM-aware and lifetime constrained optimization for multi-segment power grid networks", IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 27, no. 4, pp.940-953, April 2019 (10.1109/TVLSI.2018.2889079).

  • J27 C. Cook, S. Sadiqbatcha, Z. Sun and S. X.-D. Tan, "Reliability based hardware Trojan design using physics-based electromigration models", Integration, the VLSI Journal, vol. 66, pp. 9-15, 2019.

  • J28 Z. Sun, S. Sadiqbatcha,H. Zhao, and S. X.-D. Tan, "Saturation volume estimation for multi-segment copper interconnect wire”, IEEE Transactions on Very Large Scale Integrated Systems (TVLSI), vol. 27, no. 7, pp.1063-8210, July, 2019, DOI: https://doi.org/10.1109/TVLSI.2019.2901824

  • J29 S. Sadiqbatcha, Z. Sun and S. X.-D. Tan, "Acelerating electromigration aging: fast failure detection for nanometer ICs", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), (accepted). DOI: 10.1109/TCAD.2019.2907908.

  • H. Wang, X. Guo, S. X.-D. Tan, C. Zhang, H. Tang, Y. Yuan, “Leakage-aware predictive thermal management for multi-core systems using echo state network”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol 39, no. 7, July 2020. 10.1109/TCAD.2019.2915316

  • L. Chen,  S. X.-D. Tan,  Z. Sun, S. Peng, M. Tang and J. Mao, “Fast analytic electromigration analysis for general multi-segment interconnect wires”, IEEE Transactions on Very Large Scale Integrated Systems  (TVLSI),  vol. 28, no. 2, pp.421-432,  Feb. 2020, 10.1109/TVLSI.2019.2940197. 

  • S. Peng, E. Demircan, M. Shroff and S. X.-D. Tan, “Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis”, Integration, the VLSI Journal,  vol 70, January 2020,  https://doi.org/10.1016/j.vlsi.2019.09.012

  • Z. Sun, S. Yu, H. Zhou, Y. Liu and S. X.-D. Tan, “EMSpice: physics-based electromigration check using coupled electronic and stress simulation”, IEEE Transaction on Device and Materials  Reliability (T-DMR), vol 20, no. 2, June  2020. 10.1109/TDMR.2020.2981628

  •  L. Chen, S. X.-D. Tan, Z. Sun, S. Peng, M. Tang, J. Mao, “A fast semi-analytic approach for combined electromigration and thermomigration analysis for general multi-segment interconnects”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  May, 2020, 10.1109/TCAD.2020.2994271. 

  • S. X.-D. Tan, Z. Sun and S. Sadiqbatcha, “Interconnect electromigration modeling and analysis for nanometer ICs: from physics to full-chip”,  IPSJ (Information Processing Society of Japan) Transactions on System LSI Design Methodology (T-SLDM) (invited survey paper), Vol 13, 2020, 10.2197/ipsjtsldm.13.42

  •  X. Wang, S. Ma,  S. X.-D. Tan, C. Cook, Liang Chen, J. Yang and W. Yu, “Fast physics-based electromigration analysis for full-chip networks by efficient eigenfunction-based solution”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  2020, 10.1109/TCAD.2020.3001264. 

  •  S. Sadiqbatcha, J. Zhang, H. Zhao, H. Amrouch, J. Hankel, S. X.-D. Tan, “Post-silicon heat-source identification and machine-learning-based thermal  modeling using infrared thermal imaging”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  July 2020, 10.1109/TCAD.2020.3007541

  • H. Zhou, L. Chen and S. X.-D. Tan, “Robust power grid network design considering EM aging effects for multi-segment wires”, Integration, the VLSI Journal,  vol 77, pp. 38-47, March 2021.

Conference publications

  • C1 H. Wang, S. X.-D. Tan, X. Liu, A. Gupta, "Runtime power estimator calibration for high-performance microprocessors", Proc. Design, Automation and Test in Europe (DATE'12), pp.352-357, Dresden, Germany, March 2012.
  • C2 Z. Liu, S. X.-D. Tan, H. Wang, A. Gupta, and S. Swarup , "Compact nonlinear thermal modeling of packaged integrated systems", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'13), pp. 157-162, Yokohama, Japan, Jan. 2013
  • C3 Z. Liu, T. Xu, S. X.-D. Tan, and H. Wang, "Dynamic thermal management for multi-core microprocessors considering transient thermal effects", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'13), pp.473-478, Yokohama, Japan, Jan. 2013.
  • C4 H. Wang, S. X.-D. Tan, S. Swarup, and X. Liu, "A power-driven thermal sensor placement algorithm for dynamic thermal management", Proc. Design, Automation and Test in Europe (DATE'13), pp.1215-1220, Grenoble, France, March 2013.
  • C5 Z. Liu, S. Swarup, and S. X-D. Tan, "Compact lateral thermal resistance modeling and characterization for TSV and TSV array", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'13), San Jose, CA, Nov. 2013.
  • C6 Z. Liu, X. Huang, S. X.-D. Tan, H. Wang, H. Tang, "Distributed task migration for thermal hot spot reduction in many-core microprocessors", in Proc. International Conference on ASIC (ASICON'13), Shenzhen, China, Oct. 2013
  • C7 Y. Chi, S. X.-D. Tan, T. Yu, X. Huang and N. Wong, "Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation", Proc. Int. Symposium on Quality Electronic Design (ISQED'14), San Jose, CA, March, 2014.
  • C8 X. Huang, T. Yu, V. Sukharev, S. X.-D. Tan, "Physics-based electromigration assessment for power grid networks", Proc. IEEE/ACM Design Automation Conference (DAC'14), San Francisco, June, 2014. (Best Paper Award Nomination (12 out of 787 submissions, 1.5%))
  • C9 Z. Liu, X. Huang, V. Sukharev and S. X.-D. Tan, "EM-reliability system modeling and performance optimization for high-performance microprocessors", TECHCON'14 , Austin, TX, Sept. 2014.
  • C10 V. Sukharev, X. Huang, H. Chen and S. X.-D. Tan, "IR-drop based electromigration assessment: parametric failure chip-scale analysis", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'14), San Jose, CA, Nov. 2014.
  • C11 T. Kim, B. Zheng, H. Chen, Q. Zhu, V. Sukharev and S. X.-D. Tan, "Lifetime optimization for real-time embedded systems considering electromigration effects", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'14), San Jose, CA, Nov. 2014.
  • C12 J. Ma, H. Wang, S. X.-D. Tan, C. Zhang, H. Tang, "Hybrid dynamic thermal management method with model predictive control", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS'15), Ishigaki Island, Okinawa, Japan, Nov. 2014
  • C13 H. Chen, S. X.-D. Tan, X. Huang, V. Sukharev, "New electromigration modeling and analysis considering time-varying temperature and current densities", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'15), Chiba, Japan, Jan. 2015. .(Best Paper Award Nomination)
  • C 14 H. Chen, X. Huang, V. Sukharev, S. X.-D. Tan, T. Kim, "Interconnect reliability modeling and analysis for multi-branch interconnect trees", Proc. IEEE/ACM Design Automation Conference (DAC'15), San Francisco, June, 2015
  • C 15 T. Kim, X. Huang, V. Sukharev and S. X.-D. Tan, "A dynamic reliability management framework for dark silicon", TECHCON'2015, Austin, TX, September 2015.
  • C 16 X. Huang, V. Sukharev, J.-H. Choy, H. Chen, E. Tlelo-Cuautle and S. X.-D. Tan, "Full-chip electromigration assessment: effect of cross-layout temperature and thermal stress distributions", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey, Sept. 2015.
  • C 17 T. Kim and X. Huang, V. Sukharev, S. X.-D. Tan, "Learning-based reliability management for dark silicon systems", 6th IEEE International Workshop on Testing 3D Stacked ICs (3D-Test), Anaheim, CA, Oct., 2015.
  • C 18 K. He, X. Huang, S. X.-D. Tan, "EM-based on-chip aging sensor for detection and prevention of counterfeit and recycled ICs", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'15), Austin, TX, Nov. 2015.
  • C 19 X. Huang, V. Sukharev, T. Kim, H. Chen and S. X-D. Tan, "Electromigration recovery modeling and analysis under time-dependent current and temperature stressing", Proc. Asia South Pacific Design Automation Conference (ASP-DAC'16), Macao, China, Jan. 2016.
  • C 20 T. Kim, X. Huang, H. Chen, V. Sukharev and S. X.-D. Tan, "Learning-based dynamic reliability management for dark silicon processor considering EM effects", Proc. Design, Automation and Test in Europe (DATE'16), Dresden, March 2016.
  • C 21 X. Huang, V. Sukharev, Z. Qi, T Kim and S. X.-D. Tan, "Physics-based full-chip TDDB assessment for BEOL Interconnects", Proc. IEEE/ACM Design Automation Conference (DAC'16), Austin, TX, June, 2016.
  • C 22 T. Kim, Z. Sun, C. Cook, H. Zhao, R. Li, D. Wong and S. X.-D. Tan, "Cross-layer modeling and optimization for electromigration induced reliability", Proc. IEEE/ACM Design Automation Conference (DAC'16), Austin, TX, June 2016. (Invited)
  • C23 C. Cook, Z. Sun, T. Kim and S. X.-D. Tan, "Finite difference method for electromigration analysis of multi-branch interconnects", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'16), Lisbon, Portugal, June 2016.
  • C24 H. Wang, M. Zhang, S. X.-D. Tan, C. Zhang, Y. Yuan, K. Huang and Z. Zhang, "New power budgeting and thermal management scheme for multi-core systems in dark silicon", 29th IEEE International SoC Conference (SOCC'16), Seattle, WA Sept, 2016.
  • C25 C. Cook, Z. Sun, T. Kim and S. X.-D. Tan, "Finite difference time domain analysis of stress evolution and void growth for general interconnect wires", TECHCON'2016, Austin, TX, September 2016.
  • C26 H. Zhao, S. X.-D. Tan, H. Wang, H. Chen, "Online unusual behavior detection for temperature sensor networks", 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI'16), pp. 59-62, Pittsburg, PA, Sept. 2016.
  • C27 X. Chen, H. Chen, W. Ma, X. Li, S. X.-D. Tan, "Energy-efficient wireless temperature sensoring for smart building application", Int, Conf. Solid State and Integrated Circuit Technology (ICSICT'16), Hangzhou, China, Oct. 2016. (invited)
  • C28 Z. Sun, E. Demircan, M. Shroff, T. Kim, X. Huang, S. X.-D. Tan, "Voltage-based electromigration immortality check for general multi-branch interconnects", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'16), Austin, TX, Nov. 2016.
  • C29 T. Kim, Z. Sun, J. Gaddipati, H. Wang, H. Chen, S. X.-D. Tan, "Dynamic reliability management for near-threshold dark silicon processors", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD'16), Austin, TX, Nov. 2016. (Invited)
  • C30 L. Xu, H. Wang, S. X.-D. Tan, C. Zhang, Y. Yuan, K. Huang, Z. Zhang, "Distributed model predictive control for dynamic thermal management of multi-core systems", Int., Conf. Solid State and Integrated Circuit Technology (ICSICT'16), Hangzhou, China, Oct. 2016.
  • C31 J. Wan, H. Wang, J. He, S. X.-D. Tan, Y. Cai, S. Yang "A fast full-chip static power estimation method", Int., Conf. Solid State and Integrated Circuit Technology (ICSICT'16), Hangzhou, China, Oct. 2016.
  • C32 S. Wang, H. Zhao, S. X.-D. Sheldon Tan and M. Tahoori, "Recovery-aware proactive TSV repair for electromigration in 3D ICs", Proc. Design, Automation and Test in Europe (DATE'17), Lausenne, Switzerland, March 2017.
  • C33 X. Wang, H. Wang, J. He, S. X.-D. Tan, Y. Cai and S. Yang, "Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks", Proc. Design, Automation and Test in Europe (DATE'17), Lausanne, Switzerland, March 2017.
  • C34 Y. Yao, T. Kim H. Chen, H. Wang, E. Tlelo-Cuautle and S. X.-D. Tan, "Comprehensive detection of counterfeit ICs via on-chip sensor and post-fabrication authentication policy", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'17) Giardini Naxos - Taormina, Italy, June 2017.
  • C35 Xiaoyi Wang, Yan Yan, Jian He, S. X.-D. Tan, Chase Cook, Shengqi Yang, "Fast physics-based electromigration analysis for multi-branch interconnect trees", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD17), Irvine, CA, Nov. 2017.
  • C36 S. Wang, Zeyu Sun, Yuan Cheng, S. X.-D. Sheldon X.-D. Tan and M. Tahoori, "œPhysics-based TSV electromigratoin modeling and TSV repair for 3D power grid networks", Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD17), Irvine, CA, Nov. 2017. (invited)
  • C37 J. Peng, H. Chen, H. Zhao, Z. Sun and S. X.-D. Tan, "Dynamic temperature-aware reliability modeling for multi-branch interconnect trees", in Proc. International Conference on ASIC (ASICON17), Guiyang, China, Oct. 2017. (Best Paper Award)
  • C38 H. Zhou, Y. Sun, Z. Sun, H. Zhao and S. X.-D. Tan, "Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires", Proc. Asia South Pacific Design Automation Conference (ASP-DACÃ18), Jeju Island, Korea, Jan. 2018.

  • C39 Z. Sun, S. Sadiqbatcha and S. X.-D. Tan, "Accelerating electromigration aging for fast failure detection for nanometer ICs", Proc. Asia South Pacific Design Automation Conference (ASP-DAC18), Jeju Island, Korea, Jan. 2018. (Invited)

  • C40 S. Sadiqbatcha, C. Cook, Z Sun and S. X.-D. Tan, “Accelerating electromigration wear-out effects based on configurable sink-structured wires”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD’18), Prague, Czech Republic, July 2018. (Honorable Mention Best Paper Award)\

  • C41 C. Cook, S. Sadiqbatcha. Z. Sun and S. X.-D. Tan, “Reliability based hardware trojan design based on physics-based electromigration models”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD’18), Prague, Czech Republic, July 2018.

  • C42 H. Zhao and S. X.-D. Tan, “Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effects”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’18), San Diego, CA, Nov. 2018. (invited)

  • C43 S. Sadiqbatcha, H. Zhao, H. Amrouch, J. Henkel and S. X-D. Tan, "Hot spot identification and system parameterized thermal modeling for multi-core processors through infrared thermal imaging”, Proc. Design, Automation and Test in Europe (DATE'19), Florence, Italy, March 2019.

  • C44 Z. Sun, H. Zhou, and S. X.-D. Tan, “Dynamic reliability management for multi-core processor based on deep reinforcement learning”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'19), Lausanne, Switzerland, July 2019.

  • C45 Z. Sun, T. Kim, M. Chow, S. Peng, H. Zhou, H. Kim, D. Wong and S. X.-D. Tan, “Long-term reliability management for multitasking GPGPUs”, International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD'19), Lausanne, Switzerland, July 2019.

  • S. Sadiqbatcha, Y. Zhao, J. Zhang, H. Amrouch, J. Henkel and S. X.-D. Tan, "Machine learning based online full-chip heatmap estimation," Proc. Asia South Pacific Design Automation Conference (ASP-DAC’20), Beijing, China,  Jan. 2020. (35% acceptance rate)

  • H. Zhou, S. Yu, Z. Sun, and S. X.-D. Tan, “Reliable power grid network design framework considering EM immortalities for multi-segment wires”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’20), Beijing, China, Jan. 2020. (Invited)

  • S. Ma, X. Wang, S. X.-D. Tan, L. Chen and J. He, “An adaptive electromigration assessment algorithm for full-chip power/ground networks”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC'20), Beijing, China,  Jan. 2020.(35% acceptance rate)

  • J. Zhang, S. Sadiqbatcha, W. Jin and S. X.-D. Tan, “Accurate power density map estimation for commercial multi-core microprocessors”, Proc. Design, Automation and Test in Europe (DATE’20), Grenoble, France, March 2020. (26% acceptance rate)

  • S. Yu, H. Zhou, H. Amrouch, J. Henkel, S. X.-D. Tan, “Run-time accuracy reconfigurable stochastic computing for dynamic reliability and power management: work-in-progress”, Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’20), ESWeek 2020,  Sept  2020.

  • H. Zhou, W. Jin, and S. X.-D. Tan, “GridNet: Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’18), San Diego, CA,  Nov.  2020. (23.8% acceptance rate) (nominated as Best Paper Awards)

  • M. Kavousi, L. Chen, and S. X.-D. Tan, “Electromigration immortality check considering Joule heating effect of multi-segment wires”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’18), San Diego, CA,  Nov.  2020. (23.8% acceptance rate)

  • W. Jin, S. Sadiqbatcha, J. Zhang and S. X.-D. Tan, “Full-chip thermal map estimation for multi-core commercial CPUs with generative adversarial learning”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’18), San Diego, CA,  Nov.  2020. (invited)

  • W. Jin, S. Sadiqbatcha, Z. Sun, H. Zhou and S. X.-D. Tan, “EM-GAN: Data-driven fast stress analysis for multi-segment interconnects”, Proc. IEEE Int. Conf. on Computer Design (ICCD), Virtual, Oct. 2020.  (28% acceptance rate) (nominated as Best Paper Awards)

  • Y. Liu, S. Yu, S. Peng and S. X.-D. Tan, “Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’21), (Invited), Virtual , April 2021
  • H. Amrouch, A. B. Chowdhury, W. Jin, R. Karri, F. Khorrami, P. Krish-namurthy, I. Polian, V. M. v. Santen, B. Tan, and S. X.-D. Tan, “Machine learning for semiconductor test and reliability,” in Proceedings of the 39th IEEE VLSI Test Symposium, pp. 1–11, IEEE, Apr. 2021. (invited)
  • W. Jin, L. Chen, S. Sadiqbatch,  S. Peng and S. X.-D. Tan, “EMGraph: Fast electromigration stress assessment for interconnect trees using graph convolution networks”, Proc. IEEE/ACM Design Automation Conference (DAC’21), July, 2021.
More Project