Biographic sketch of Prof. Sheldon Tan

• Dr. Sheldon Tan is a Full Professor in the Department of Electrical and Computer Engineering, University of California at Riverside. He also is a cooperative faculty member in the Department of Computer Science and Engineering at UCR. He received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. He was a visiting professor of Kyoto University as a JSPS Fellow in 2017. He also was a Visiting Professor of Fudan University and Tsinghua University, China. He is an IEEE Fellow. 
• He was a faculty member in Department of Electrical Engineering, Fudan University from 1995 to 1996. He worked for Monterey Design Systems Inc. (now Synopysis), CA, from 1999 to 2001 and Altera Corporation CA, from 2001 to 2002. Since 2002, he has been with the Department of Electrical Engineering, University of California at Riverside, CA. 
• Dr. Tan research interests include several aspects of design automation for VLSI integrated circuits : (1) Machine and deep learning for VLSI reliability modeling and optimization, (2) VLSI long-term reliability, resilient systems, fault tolerant computing, reliability-aware design and management at circuit and system levels; (3) Parallel computing and analysis on heterogeneous and accelerator-rich (GPUs) platforms; (4) Machine learning based thermal modeling, optimization and dynamic thermal management at circuit, chip and board levels;  (5) Advanced VLSI design techniques for machine and deep learnings; (6) Statistical and compact modeling and optimization for VLSI interconnects. 
• He has published over 310 journal and conference papers and gave over 110 invited presentations, tutorials and short courses at conferences and workshops. He co-authored four books: Symbolic Analysis and Reduction of VLSI Circuits published by Springer/Kluwer in 2005, Advanced Model Order Reduction Techniques for VLSI Designs by Cambridge University Press published in 2007; Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Design by Springer Publishing in 2012 and "Advanced Symbolic Analysis for VLSI Systems -- Methods and Applications by Springer in 2014.
• He received NSF CAREER Award in 2004. Dr. Tan received the Best Paper Award from 2007 IEEE International Conference on Computer Design. Dr. Tan received the Best Paper Award from 2007 IEEE International Conference on Computer Design (ICCD07), the Best Paper Award from 1999 IEEE/ACM Design Automation Conference, Best Paper Award from IEEE International Conference on ASIC (ASICON17), The honorable mention Best Paper Award from International conf. on Synthesis, modeling, analysis and simulation methods and applications to circuit design (SMACD18) and Best Paper Award from Int., Conf. Solid State and Integrated Circuit Technology (ICSICT'18). He also receives a few Best Paper Award Nominations from IEEE/ACM Design Automation Conferences in 2005, 2009 and 2014 and one Best Paper Award nomination from ASPDAC in 2015 and one from International Conference on Modern Circuits and Systems Technologies (MOCAST18). He received the UC Regent's Faculty Fellowship in 2004 and 2006 and Academic Senate COR (committee on Research) Fellowship from UCR in 2008 and 2013. One of his papers was one of Top 10 of Downloaded Articles in ACM Transaction on Design Automation of Electronic Systems (TODAES) in 2010. He also received the Best Graduate Award and a number of Excellent College Student Scholarships from Fudan University.
• He now is serving as the Editor-In-Chief for Integration, The VLSI Journal. He has served or is serving  as an Associate Editor for following  journals: IEEE Transaction on VLSI Systems (TVLSI), ACM Transaction on Design Automation of Electronic Systems (TODAES) and Microelectronics Reliability and MDPI Electronics, Microelectronics and Optoelectronics Section. He served as the technical program committee (TPC) Chair for ASPDAC 2021, TPC Vice Chair for ASPDAC 2020. He is serving (or has been served) on technical program committee for DAC, ICCAD, DATE, ISLPED, ASPDAC, ICCD, ISQED, SMACD, ASICON, ICSICT, FAC and the ACM/SIGDA Outstanding PhD Dissertation Award Selection Committee and IEEE Technical Committee on Cyber-Physical System. Dr. Tan is an IEEE Fellow. He holds two patents in United States and 5 patents in China.

IEEE Style Biographical Sketch of Prof. Sheldon Tan

• {Sheldon X.-D. Tan} (SM-96, M-99, SM-06, F-25) received his B.S. and M.S. degrees in electrical engineering from Fudan University, Shanghai, China in 1992 and 1995, respectively and the Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. He is a Professor in the Department of Electrical Engineering, University of California, Riverside, CA. He is the Associate Director of Compute Engineering Program (CEN) at Bourn College of Engineering at UC Riverside since 2009. He also is a cooperative faculty member in the Department of Computer Science and Engineering at UCR. He is an IEEE Fellow. 
• His research interests include: (1) Machine and deep learning for VLSI reliability modeling and optimization, (2) VLSI long-term reliability, resilient systems, fault tolerant computing, reliability-aware design and management at circuit and system levels; (3) Parallel computing and analysis on heterogeneous and accelerator-rich (GPUs) platforms; (4) Machine learning based thermal modeling, optimization and dynamic thermal management at circuit, chip and board levels;  (5) Advanced VLSI design techniques for machine and deep learnings; (6) Statistical and compact modeling and optimization for VLSI interconnects. 
• He co-authored five books: "Symbolic Analysis and Reduction of VLSI Circuits" published by Springer/Kluwer in 2005," Advanced Model Order Reduction Techniques for VLSI Designs" by Cambridge University Press published in 2007; "Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Design" by Springer Publishing in 2012 and "Advanced Symbolic Analysis for VLSI Systems -- Methods and Applications" by Springer Publisher in 2014, and "VLSI Systems Long-Term Reliability -- Modeling, Simulation and Optimization" by Springer Publisher, 2019.
• He received Outstanding Oversea Investigator Award from the National Natural Science Foundation of China (NSFC) in 2008. He received NSF CAREER Award in 2004. Dr. Tan received the Best Paper Award from 2007 IEEE International Conference on Computer Design (ICCD07), the Best Paper Award from 1999 IEEE/ACM Design Automation Conference. Best Paper Award from IEEE International Conference on ASIC (ASICON17), The honorable mention Best Paper Award from International conf. on Synthesis, modeling, analysis and simulation methods and applications to circuit design (SMACD18). He also receives three Best Paper Award Nomination from IEEE/ACM DAC in 2005, 2009 and 2014 and one Best Paper Award nomination from ASPDAC in 2015. one from MOCAST in 2018.
• He has been  serving as the Editor-In-Chief for Integration, The VLSI Journal since 2016,  He has served or is serving  as an Associate Editor for following  journals: IEEE Transaction on VLSI Systems (TVLSI), ACM Transaction on Design Automation of Electronic Systems (TODAES) and Microelectronics Reliability and MDPI Electronics, Microelectronics and Optoelectronics Section. He served as the technical program committee (TPC) Chair for ASPDAC 2021, TPC Vice Chair for ASPDAC 2020. He is serving (or has been served) on technical program committee for DAC, ICCAD, DATE, ISLPED, ASPDAC, ICCD, ISQED, SMACD, ASICON, ICSICT, FAC and the ACM/SIGDA Outstanding PhD Dissertation Award Selection Committee.