VLSI System and Computation Lab

WE ENGINEER EXCELLENCE

Machine Learning Approach for Fast  Electromigration Analysis and Full-Chip Assessment

November 02, 2021

 

Principle Investigators

Graduate Students

Current Students

  • Sheriff Sadiqbatcha 
  • Shuyuan Yu
  • Wentian Jin
  • Jinwei Zhang
  • Mohammadamir Kavousi
  • Yibo Liu
  • Liang Chen (post-doc, SJTU)
  • Subed Lamichlane 
  • Jincong Lu

Graduate Students (graduated)

  • Han Zhou (First job: Synopsys)

Funding

We appreciate the following funding agencies for their generous supports of this project.

  1. National Science Foundation CISE CCF Core Small program (CCF-1816361), “SHF: Small:  Machine Learning Approach for Fast  Electromigration Analysis and Full-Chip Assessment, $500,000,  Oct. 1st, 2020  to Sept 30th, 2023, single PI.

The related project

Project Descriptions

Background

Electromigration (EM) has become one of the most critical design issues and limiting factors for nanometer VLSI designs because of the shrinking size and increasing current density of the interconnects as technology scales down to sub 7nm. It was expected that the future chips will show signs of reliability-induced aging much faster than the previous generations. Due to its importance, many advances have been made recently in the EM modeling and assessment techniques. However, fast and full-chip level EM analysis and validation still remain achallenging proble as completely modeling the EM failure process requires solving partial differential equations of hydrostatic stress in large interconnects. This will become even more difficult for full-chip level EM sign-off analysis.  At the same time, machine learning, especially deep learning based on deep neural networks (DNN) such as convolutional neural networks (CNN) and generative adversarial networks (GAN) is gaining much attention due to transformative successes in the many cognitive tasks such as face detection, speech recognition. However, how to apply the deep learning techniques to learn and encode laws of physics and help to solve nonlinear partial differential equations still remains in its infancy. But recently proposed Physics-informed Neural Networks (PINN) and the success of using GAN for fast lithographical simulation for physical layout design provide some promises in this direction. As today's deep learning methods are essentially universal nonlinear modeling, feature extraction and representation tools based on the stochastic back propagation optimization scheme, they can help solve to many of the modeling and analysis challenging facing the design tool industry.  This project will develop deep learning and data-driven based EM analysis, modeling and full-chip assessment algorithms for EM-aware physical optimization techniques and dynamic reliability management techniques for VLSI chips in the nanometer regime.

Publications

Journal publications

  • Z. Sun, S. Yu, H. Zhou, Y. Liu and S. X.-D. Tan, “EMSpice: physics-based electromigration check using coupled electronic and stress simulation”, IEEE Transaction on Device and Materials  Reliability (T-DMR), vol 20, no. 2, June  2020. 10.1109/TDMR.2020.2981628

  •  L. Chen, S. X.-D. Tan, Z. Sun, S. Peng, M. Tang, J. Mao, “A fast semi-analytic approach for combined electromigration and thermomigration analysis for general multi-segment interconnects”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  May, 2020, 10.1109/TCAD.2020.2994271. 

  • S. X.-D. Tan, Z. Sun and S. Sadiqbatcha, “Interconnect electromigration modeling and analysis for nanometer ICs: from physics to full-chip”,  IPSJ (Information Processing Society of Japan) Transactions on System LSI Design Methodology (T-SLDM) (invited survey paper), Vol 13, 2020, 10.2197/ipsjtsldm.13.42

  •  X. Wang, S. Ma,  S. X.-D. Tan, C. Cook, Liang Chen, J. Yang and W. Yu, “Fast physics-based electromigration analysis for full-chip networks by efficient eigenfunction-based solution”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  2020, 10.1109/TCAD.2020.3001264.

  • H. Zhou, L. Chen and S. X.-D. Tan, “Robust power grid network design considering EM aging effects for multi-segment wires”, Integration, the VLSI Journal,  vol 77, pp. 38-47, March 2021.
  • H. Zhou, Y. Liu, W. Jin and S. X.-D. Tan, “GridNetOpt: Fast full-chip EM-aware power grid optimization accelerated by deep neural networks”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted, 10.1109/TCAD.2022.3206397.
  • L. Chen, S. Sadiqbatcha, H. Amrouch and S. X.-D. Tan, “Electrothermal simulation and optimal design of thermoelectric cooler using analytic approach”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems(TCAD), vol. 41, no. 9, page: 3066-3077, 2022, 10.1109/TCAD.2021.3120533
  • Zhang, S. Sadiqbatcha and S. X.-D. Tan, “Hot-Trim: Thermal and reliability management for commercial multi-core processors considering workload dependent hot spots”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted.  10.1109/TCAD.2022.3216552.

Conference publications

  • H. Zhou, S. Yu, Z. Sun, and S. X.-D. Tan, “Reliable power grid network design framework considering EM immortalities for multi-segment wires”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC’20), Beijing, China, Jan. 2020. (Invited)
  • S. Ma, X. Wang, S. X.-D. Tan, L. Chen and J. He, “An adaptive electromigration assessment algorithm for full-chip power/ground networks”, Proc. Asia South Pacific Design Automation Conference (ASP-DAC'20), Beijing, China,  Jan. 2020.(35% acceptance rate)
  • S. Yu, H. Zhou, H. Amrouch, J. Henkel, S. X.-D. Tan, “Run-time accuracy reconfigurable stochastic computing for dynamic reliability and power management: work-in-progress”, Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES’20), ESWeek 2020,  Sept  2020.

  • W. Jin, S. Sadiqbatcha, Z. Sun, H. Zhou and S. X.-D. Tan, “EM-GAN: Data-driven fast stress analysis for multi-segment interconnects”, Proc. IEEE Int. Conf. on Computer Design (ICCD), Virtual, Oct. 2020.  (28% acceptance rate) (nominated as Best Paper Awards.

  • H. Zhou, W. Jin, and S. X.-D. Tan, “GridNet: Fast date-driven EM-induced IR drop prediction and localized fixing for on-chip power grid networks”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’20), San Diego, CA,  Nov.  2020. (23.8% acceptance rate) (nominated as Best Paper Awards)
  • M. Kavousi, L. Chen, and S. X.-D. Tan, “Electromigration immortality check considering Joule heating effect of multi-segment wires”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’20), San Diego, CA,  Nov.  2020. (23.8% acceptance rate)
  • S. Peng, W. Jin, L. Chen, and S. X.-D. Tan, "Data-driven fast electrostatics and TDDB aging analysis", Proc. of the 2020 ACM/IEEE Workshop on Machine Learning for CAD (MLCAD'20), Virtual Event, Nov. 2020
  • Y. Liu, S. Yu, S. Peng and S. X.-D. Tan, “Runtime Long-Term Reliability Management Using Stochastic Computing in Deep Neural Networks”, Proc. Int. Symposium. on Quality Electronic Design (ISQED’21), (Invited), Virtual , April 2021
  • H. Amrouch, A. B. Chowdhury, W. Jin, R. Karri, F. Khorrami, P. Krish-namurthy, I. Polian, V. M. v. Santen, B. Tan, and S. X.-D. Tan, “Machine learning for semiconductor test and reliability,” in Proceedings of the 39th IEEE VLSI Test Symposium, pp. 1–11, IEEE, Apr. 2021. (invited)
  • W. Jin, L. Chen, S. Sadiqbatch,  S. Peng and S. X.-D. Tan, “EMGraph: Fast electromigration stress assessment for interconnect trees using graph convolution networks”, Proc. IEEE/ACM Design Automation Conference (DAC’21), July, 2021.
  • S. Lamichhane, S. Peng, W. Jin and S. X.-D. Tan, "Fast electrostatic analysis for VLSI aging based on generative learning", Proc. of the 2020 ACM/IEEE Workshop on Machine Learning for CAD (MLCAD'21), Virtual Event, Nov. 2021.
  • M. Kavousi, L. Chen and S. X.-D. Tan, "Fast electromigration stress analysis considering spatial Joule heating effects”,  Proc. Asia South Pacific Design Automation Conference (ASP-DAC’22), virtual,  Jan. 2022.
  • W. Jin, L. Chen, S. Lamichhane,  M. Kavousi and S. X.-D. Tan, “HierPINN: Fast learning-based electromigration analysis for multi-segment interconnects using hierarchical physics-informed neural networks”, Proc. IEEE/ACM International Conf. on Computer-Aided Design (ICCAD’22), San Diego, CA,  Nov.  2022.
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