MSLAB announced the circuit complexity reduction tool – UiMOR V1.0. UiMOR can reduce general parasitic RLC circuits in the post-layout design stage to boost the verification process. It accepts general SPICE netlist and produces the reduced SPICE-compatible netlists, thus it fits seamless with existing VLSI design verification flow. UiMOR will be announced in the ICSICT conference in Shanghai, Nov. 4, 2010.  UiMOR V1.0 Linux executable code is available now from MSLAB.