Dr. Shijie Wen from Cisco System Corporation visited MSLAB and discussed some research topics for potential collaborations. Dr. Wen is a distinguished engineer in Cisco and his research interests focus on the reliability and resilience chip design and analysis.
Dr. William H. Joyner, Jr. from Semiconductor Research Corporation visited EE department at UCR. Dr. Joyner is Director of Computer-Aided Design and Test at the Semiconductor Research Corporation. He presented a department colloquium talk titled Funding for University Research: What Industry Wants and How to Get Their Money. After the talk, he also visited the...
Dr. Ashish Gupta, who is the Manger of Thermal and Fluids Core Competency group at Assembling and Testing Technology Development (ATTD) organization at Intel Corporation visited EE Department and MSLAB at UCR today. He also presented a department Colloquium titled Ò Technical Considerations during Packaging and Test at Intel CorporationÓ. Dr. Gupta is a collaborator...
MSLAB's journal paper published on TODAES ( ACM Transaction on Design Automation of Electronic Systems) in Feb. 2010 has been one of Top 10 Downloaded Articles published in 2010. D. Li, S. X.-D. Tan, E. H. Pacheco, M. Tirumala , Parameterized architecture-level thermal modeling for multi-core microprocessors , ACM Transaction on Design Automation of Electronic...
International Workshop on Emerging Circuits and Systems ( IWECS11 ) is announced. The workshop will be held in Hangzhou, Zhejiang Province, China from Aug. 4-5, 2011.
UC Riverside has been selected as a CUDA Teaching Centers (2010-2011) by Nvidia Corporation, CA,based on demonstrated commitment of UCR Faculty, especially Prof. Sheldon Tan, to advancing the state of parallel education using CUDA C/C++. CUDA Teaching Center comes with equipment donations, funding support for course development, course material assistance and software license from Nvidia...
MSLAB announced the circuit complexity reduction tool – UiMOR V1.0. UiMOR can reduce general parasitic RLC circuits in the post-layout design stage to boost the verification process. It accepts general SPICE netlist and produces the reduced SPICE-compatible netlists, thus it fits seamless with existing VLSI design verification flow. UiMOR will be announced in the ICSICT...
Ph.D. student Duo Li has successfully defended his Ph.D. thesis today. His thesis is titled Modeling, Characterization and Simulation of On-Chip Power Delivery Networks and Temperature Profile on Multi-Core Microprocessors. Duo is the 8 th Ph.D. student graduated from MSLAB since 2002. Duo joined Synposys in Mountain View, CA in July 2010. We wish Duo...
Prof. Sheldon Tan visited the ATTD (Assembling and Testing Technology Development) group at Intel Corporation at Chandler, AZ. ATTP group develops all the advanced packaging and testing technologies used in Intel Corporation. Prof. Tan presented an invited talk titled Chip-Level Thermal Modeling and Characterizations for Single and Multi Core Processor Designs.
Three new Ph.D. student joined MSLAB this year. Zao Liu, who graduated from Northeast Univ (BS) and Xi'an Jiaotong Univ (BS) and Sahana Swarup, who graduated from Ramaiah Institute of Technology (BS) and California State Univ at Northridge (MS). Welcome them and hope they can be successful in their Ph.D. study at UCR.
Prof. Sheldon Tan received a new research grant from National Science Foundation CISE division CCF Core. The 3-year project is SHF: Small: GPU-Based Many-Core Parallel Simulation of Interconnect and High-Frequency Circuits. (CCF-1017090). Prof. Tan is the single PI for this grant. The project will focus on the GPU based parallel simulation of large interconnect and...
M.S. student Ryan Rakid has successfully defended his M.S. thesis titled Comparison of Recent Algorithms in Model Order Reduction of Interconnect Circuits, Congratulation on Ryan. We wish Ryan the best and more success in his future career.
The second International Workshop on Emerging Circuits and Systems (IWECS10) , was held successfully in Hefei, China, Dr. Tan is the co-chair of the IWECS10. IWECS10 attracted more 30 international experts from US, Canada, China and Taiwan. The workshop has 16 invited talks covering emerging new non-silicon devices to system level designs. Dr. Tan also...
Prof. Sheldon Tan visited the State-Key Lab of ASIC and Systems at Fudan Univ. Shanghai, China. He also presented an invited talk titled Statistical Analysis of Full-Chip Leakage Power in Nanometer VLSI Systems.
h.D. Student Duo Li accepted an offer from Synopysis IC Compiler group as a Sr. R & D Engineer in July 2010. Synopysis is a leading electronic design automation and solution company in the world. We wish Duo best and more successes in his future endeavor.
M.S. student, Thom Eguia successfully defended his M.S. thesis titled "Package-level Thermal Behavioral Modeling for Multi-Core Microprocessors". Congratulation on Thom. We wish Thom best and more success in his future career.
Dr. Boyuan Yan's paper title Passive rational interpolation based reduction via Caratheodory extension for general systems has been accepted by IEEE Transaction on Circuit and System II(TCAS-II). Boyuan is now working as a post-doc at Texas A&M University.
Prof. Sheldon Tan presented an invited talk titled Architecture-level Thermal Modeling and Simulation for Multi-Core Chip Design in 2nd Nanoelectronics and Advanced Design Seminar at INAOE (Institute National Astrophysics, Optical and Electrics) at Puebla, Mexico.
